1. Field of the Invention
The present invention relates to a semiconductor structure having a metal gate and a method of forming the same, and more particular to a semiconductor structure having a broadened opening and a method of forming the same.
2. Description of the Prior Art
The performance of semiconductors has increased year after year with the critical dimensions and the advance of large-scale integrated circuits. In the field of semiconductor fabrication, since poly-silicon material has a strong heat resistance, the poly-silicon material is commonly used to fabricate the gate structure of the semiconductor structure, especially for the fabrication of the gate electrode of the metal oxide semiconductor transistor. In addition, the gate electrode made of poly-silicon may prevent dopings into the channel region during the ion implantation process. In addition, in the high-temperature environment, the poly-silicon gate electrode may endure high-temperature annealing processes, such that the self-aligned source region and drain region are formed. On the contrary, the poly-silicon gate still has many disadvantages which may not be conquered until now. Firstly, as compared with the poly-silicon material and most metal materials, poly-silicon material is a kind of semiconductor material having high electrical resistance, such that the operational speed of the poly-silicon gate electrode having high electrical resistance is still low with respect to the metal conducting line. In order to solve the problem of high electrical resistance and the corresponding low operational speed, the gate electrode made of poly-silicon material usually needs to utilize a silicide process step, such that the operational speed may be promoted to expected goals. Consequently, the forming of a semiconductor structure having the metal gate of the present invention becomes an important method for solving the aforementioned problems.
However, since line width of the semiconductor structure is minimized to a limitation, the integration process of the semiconductor structure having a metal gate has more challenges and problems. Please refer to FIG. 1 and FIG. 2, FIG. 1 and FIG. 2 are schematic diagrams illustrating the forming method of the semiconductor structure having a metal gate. As illustrated in FIG. 1, firstly, a semiconductor substrate 10 is provided. Subsequently, a gate structure 12 is formed on the semiconductor substrate 10, wherein the gate structure 12 includes a dummy patterned poly-silicon layer 12a and a patterned gate dielectric layer 12b. Then, a light doping source region 13 and drain region 13 is formed on the semiconductor substrate 10. The offset spacer 14 and the spacer 16 are formed on the peripheral side wall of the gate structure 12. Afterwards, a source region 18a and a drain region 18b are formed. Finally, a interlayer dielectric layer 17 is formed and a portion of the interlayer dielectric layer 17 on top of the dummy patterned poly-silicon layer 12a is removed by virtue of a chemical mechanical polishing/planarization (CMP) process, such that the exposed dummy patterned poly-silicon layer 12a is disposed in the well 19 defined by the offset spacer 14 and the patterned gate dielectric layer 12b. 
Afterwards, as illustrated in FIG. 2, the dummy patterned poly-silicon layer 12a is etched to expose the well 19, and a work function layer 21 and a gate conductive layer 20 are directly deposited in the well 19, such that the gate conductive layer 20 serving as a metal gate is electrically connected to other metal interconnect lines to form a transmission route of the gate electrode electrical signals. Because the aspect ratio of the well 19 of the gate structure 12 of the semiconductor structure is a limitation especially when minimized to 28 nm, a preferred step converge is not provided according to the method of depositing the metal gate conductive layer nowadays, such that the problems of overhang or void may occur to seriously influence the filling quality of the gate conductive layer.
In view of this, the metal gate conductive layer of the conventional semiconductor structure having a metal gate has non-ideal drawbacks. In addition, the problems of void and overhang may not be solved according to the present manufacturing techniques.